1. Field of the Invention
The invention relates to the fabrication of structures in integrated circuit devices, and more particularly to a method of forming interconnects using a damascene process.
2. Description of the Related Art
Fabrication of integrated circuits (ICs) utilizes multilevel wiring structures to interconnect regions within devices and one or more devices within the ICs. Currently, damascene technology is a useful method for forming such structures and is widely applied in semiconductor industry.
Damascene is an interconnection fabrication process in which trenches are formed in an insulating layer and filled with metal to form the wiring layers. FIGS. 1a to 1d are cross-sections of the conventional method for forming a damascene structure. In FIG. 1a, a substrate 100, such as a silicon wafer, having metal wiring layers 102 therein, is provided. Next, a sealing layer 104, such as silicon nitride, is deposited on the substrate 100 to cover the wiring layers 102. Thereafter, an intermetal dielectric (IMD) layer 106 and a capping layer 108 are successively deposited over the sealing layer 104. The IMD layer 106 can be low k dielectric material, such as spin on glass (SOG), fluorinated SiO2 (FSG), hydrogen silsesquioxane (HSQ), FLARE, or SiLK. Moreover, the capping layer 108 is used for protect the IMD layer 106 and can be silicon oxide. Next, a hard mask layer 110, such as silicon nitride, coated with a photoresist layer 112 having trench patterns, is formed on the capping layer 108. The hard mask is anisotropically etched using the photoresist layer 112 as a mask to form openings 114 therein.
Next, in FIG. 1b, after the photoresist layer 112 is removed, the exposed portions of the capping layer 108 under the openings 114 are etched by conventional reactive ion etching (RIE) to expose the insulating layer 106.
Unfortunately, the etching selectivity between hard mask layer 110 and capping layer 108 and the IMD layer 106 is poor, resulting in a tapered hard mask layer 110, as shown in FIG. 1b. When the insulating layer 106 is etched using the tapered hard mask layer 110 as an etch mask, trenches 116, having sloped profile, are formed therein. That is, undesired critical dimension of the trenches 116 causes the electrical properties of devices to change. The regions surrounded by dotted lines indicate the desired profile of hard mask layer 110.
In FIG. 1c, after-the tapered hard mask layer 110 is removed, the capping layer 108 is lost, especially in the region 117 between dense trenches 116.
Finally, In FIG. 1d, standard pre-cleaning is performed by inductively coupled plasma (ICP) process (in-situ argon ion sputter etching) to remove native oxide or polymer residue (not shown). Next, a conductive layer (not shown), such as copper, is formed on the capping layer 108 and fills the trenches 116. Commonly, a conformable barrier layer (not shown) is formed over the capping layer 108 and the surfaces of the trenches 116. Thereafter, the excess conductive and barrier layers are removed by chemical mechanical polishing (CMP) using the capping layer 108 as an etching stop to form damascene structures 118.
However, the loss of capping layer 108 between dense trenches 116 induces dishing and results in metal bridging 120 after CMP, degrading the reliability of devices.
In order to solve the problems, it has been suggested to use metal hard mask, such as titanium nitride or tantalum nitride, thereby increasing the etching selectivity between the hard mask and capping layer and IMD layer. The trenches having vertical profile can be achieved by metal hard mask. Unfortunately, titanium or tantalum atoms of the hard mask are sputtered out by argon ions during pre-cleaning and deposited on the inner wall of the ICP chamber, causing the ICP etch chamber to fail.
Accordingly, an object of the invention is to provide a method for forming a damascene structure to protect the low k dielectric layer from unintended etching or removal, thereby preventing critical dimension (CD) variation and metal bridging.
Another object of the invention is to provide a method for forming a damascene structure to avoid ICP etch chamber failure after pre-cleaning.
To achieve the and other advantages, the invention provides a novel method for forming a damascene structure. First, an insulating layer is deposited on a substrate. A capping layer and a hard mask layer are successively formed on the insulating layer. Subsequently, the hard mask layer is etched to form at least one opening using the capping layer as an etching stop layer. A conformable metal layer is formed over the hard mask layer and the surface of the opening, and the metal layer is then anisotropically etched to form a metal spacer over the sidewall of the opening. Next, the capping layer and the underlying insulating layer under the opening are etched to form a trench therein. Next, the hard mask layer and the metal spacer are removed. Finally, the trench is filled with the conductive layer to complete the damascene structure after cleaning the substrate by argon ion sputter etching in an inductively coupled plasma (ICP) chamber.
The insulating layer contains a low k dielectric layer. The capping layer can be undoped silicon glass (USG) and the hard mask layer can be silicon nitride or silicon carbide. Moreover, the metal spacer has a thickness about 100xcx9c500 xc3x85 and can be aluminum or a barrier material of titanium nitride (TiN) or tantalum nitride (TaN).